In a personal computer structure, in addition to the central unit processor (CPU), the core logic chip and the memory module have most effect on the data-processing performance. Please refer to FIG. 1A which is a schematic circuit block diagram showing the connection of a core logic chip and a memory module. With a double-date-rate (DDR) transmission specification, when the core logic chip 10 transmits a parallel data to the memory module 11, a strobe signal and a parallel data signal TX_D are transmitted to the memory module 11 simultaneously for facilitating the memory module 11 to read the data. The associated signals described as above is shown in FIG. 1B. Ideally, the rising edge or falling edge of each strobe signal is positioned right in the middle of a data bit of the parallel data signal TX_D, thereby assuring of correct data transmission.
In general, four output clock signals P0, P1, P2 and P3 with a phase difference of 90 degrees between every two adjacent signals, as shown in FIG. 2A, are required. A delay phase-locked loop (PLL) device can be used to achieve this purpose. Referring to FIG. 2B, the delay PLL device includes a controlled delay circuit 21, a phase detector 22 and a control circuit 23. The controlled delay circuit 21 consists of four delay lines 211, 212, 213 and 214, each of which comprises a plurality of delay units (not shown). A reference clock signal CLK is transmitted through and processed by the four controlled delay lines 211, 212, 213 and 214 to generate the four output clock signals P0, P1, P2 and P3. The four output clock signals have the phase difference of 90 degrees to each other. In order to keep in phase with the reference clock signal CLK, the output clock signal P0 is transmitted to the phase detector 22 along with the reference clock signal CLK. If the phase detector 22 detects an earlier phase of the reference clock signal CLK than the output clock signal P0, a counting-down adjusting signal is asserted. On the contrary, i.e. the phase of the reference clock signal CLK is later than that of the output clock signal P0, a counting-up adjusting signal is asserted. Once either of the adjusting signals is transmitted to the control circuit 23, a counted value CNT will be outputted to each of the controlled delay lines 211, 212, 213 and 214 by the control circuit 23 in response to the adjusting signal. The counted value represents the involving number n of delay units for each delay line. In other words, the delay time in each delay line can be controlled according to the counted value CNT.
For example, in the case that the phase of the reference clock signal CLK is earlier than that of the output clock signal P0, it means that the delay period effected by the controlled delay circuit 21 is too long. Thus the phase detector 22 asserts the counting-down adjusting signal, and the control circuit 23 outputs a counted value CNT=n−1 rather than CNT=n. In response to the reduced counted value, the delay period of each controlled delay line is simultaneously shortened, thereby adjusting the phase of the output clock signal.
The phases of the four output clock signals P0, P1, P2 and P3 are assured to be evenly distributed by 90-degree partition because the four controlled delay lines are imparted to the same counted value. Unfortunately, this will result in insufficient accuracy of signal delay because the phases are always adjusted by four delay units at one time. The insufficient accuracy may deteriorate the performance of the circuit particularly when the transmission rate is getting higher and higher. Further, in spite the parallel data signal TX_D initially generated by the source 101 according to the prior art is substantially perfect, the signals may be skewed or interfered to some extent when they have been outputted from the source 101 and forwarded to the I/O pad 102 via various transmission paths. Therefore, the strobe signal and parallel data signal outputted by the I/O pad 102 may have waveforms as shown in FIG. 2C rather than those shown FIG. 1B. That is, the rising edge and falling edge of the strobe signal may deviate from the middle position of the parallel data signal TX_D. Accordingly, errors may happen for the memory module 11 to receive data. This problem may be even serious when the transmission rate is getting higher and higher.